M. Tech VLSI Design - COURSE DETAILS


  

TIFAC-CORE at SASTRA Deemed University  

     


M. Tech VLSI Design - COURSE DETAILS
(2006 - 2008)

SYLLABUS

MVLD101R01 - Basics of VLSI

L - 4, T - 0, P - 0 ( 60 Periods )

UNIT –  I

Introduction to CMOS circuits: MOS transistors, MOS switches, CMOS logic: Inverter, combinational logic, NAND, NOR gates, compound gates, Multiplexers. Memory: Latches and registers. Circuit and system representations: Behavioral, structural and physical representations.

UNIT – II

MOS transistor theory: NMOS, PMOS enhancement mode transistors,  Threshold voltage, body effect, MOS device design equations, MOS models, small signal AC characteristics, CMOS inverter DC characteristics, static load MOS inverters, Bipolar devices - advanced MOS modeling – large signal and small signal modeling for BJT.

UNIT – III

LOW – VOLTAGE LOW  POWER VLSI CMOS CIRCUIT DESIGN  CMOS invertor – Characteristics – Power dissipation. Capacitance estimation. CMOS static logic design, Logic styles.

UNIT – IV

Circuit characterization and performance estimation: Estimation of resistance, capacitance, inductance. Switching characteristics, CMOS gate transistor sizing, power dissipation, sizing routing conductors, charge sharing, Design margining yield, reliability. Scaling of MOS transistor  dimensions.

UNIT – V

CMOS circuit and logic design: CMOS logic gate design,   physical design of simple logic gates. CMOS logic structures. Clocking strategies, I/O Structures.

References

1.      Weste, Eshraghian,  “Principles of CMOS VLSI design”, 2nd Edition Addison Wesley, 1994.

2.      Douglas A Pucknell and Kamaran Eshragian, “ Basic VLSI design “, 3rd edition, PHI, 1994.

3.      BELLAOUR & M.I.ELAMSTRY, “Low – Power Digital VLSI Design, Circuits and Systems”,

         Kluwer Academic Publishers, 1996.

4.      S.IMAM & M.PEDRAM, “Logic synthesis for Low – Power VLSI Designs”, Kluwer Academic  

       publishers, 1998.

5.      B.G.K.YEAP, “Practical Low Power Digital VLSI Design”, Kluwer Academic publishers, 1998.

MVLD102R01 - Semiconductor Physics & Processing

L - 4, T - 0, P - 0 ( 60 Periods )

Unit – I  Introduction to semiconductor devices

Introduction- material conductivity - Quantum mechanics - energy bands - crystalline structures - Density of states - band structures - Fermi - Dirac function - material classification - Band structure - electrons and holes - doping - Scattering - mobility - Diffusion transport - Einstein relation - Carrier generation and recombination- continuity equation.

Unit –II  Crystal Growth, Wafer Preparation, Epitaxy and   Oxidation

Review of Semiconductor theory - Electronic Grade Silicon - Czochralski Crystal Growing - Silicon Shaping Processing consideration - Vapor Phase Epitaxy   - Molecular Beam Epitaxy   - Silicon on Insulators – Epitaxial Evaluation – Growth Mechanism and Kinetics – Thin Oxides – Oxidation Techniques and Systems – Oxide Properties.

Unit –III  Lithography and Relative Plasma Etching

Optical Lithography – Electron Lithography – X-Ray Lithography - Ion Lithography Plasma - Properties – Feature Size - Control and Anisotropic Etch Mechanism – Relative Plasma Etching Techniques and Equipments.

Unit – IV  Deposition , Diffusion, Lon Implementation And Metallization

Deposition Processes – Polysilicon – Plasma Assisted Deposition – Models of Diffusion in Solids – Fick’s One Dimensional Diffusion Equation – Atomic Diffusion Mechanism – Measurement Techniques – Range Theory – Implantation Equipment. Annealing Shallow Junction – High Energy Implantation – Physical Vapor Deposition – Patterning.

Unit – V   VLSI Process  Integration, Analytical, Assembly Techniques And Packaging Of VLSI  Devices

NMOS IC Technology – CMOS IC Technology – MOS Memory IC Technology – Bipolar IC Technology – IC Fabrication. Analytical Beams – Beams Specimen Interaction – Chemical Methods – Package Types baking Design Considerations – VLSI  Assembly Technology – Package Fabrication Technology.

References

  1. S.M.Sze, “VLSI Technology “, McGraw-Hill, 2nd  edition, 1988

  2. Duoglas A Pucknell and Kamaran Eshragian,” Basic VLSI design”, 3rd edition, PHI, 1994.

  3. Wayne wolf, “ Modern VLSI design”, 2nd edition, Prentice Hall Ptr, 1998.

MVLD103R01 - Modelling of Digital Systems using HDL

L - 4, T - 0, P - 0 ( 60 Periods )

UNIT – I   Introduction to PLDs & FPGAs

ROMs, Logic array (PLA), Programmable array logic, GAL,  bipolar PLA, NMOS PLA, PAL 14L4, Xilinx logic cell array (LCA) – I/O Block – Programmable interconnect – Xilinx – 3000 series and 4000 series FPGAs. Altera CPLDs, altera FLEX 10K series PLDs.

UNIT – II   Placement and routing

Mincut based placement – iterative improvement placement– Routing: Segmented channel routing – Maze routing – Routability and routing resources – Net delays.

UNIT – III   Introduction to VHDL

Digital system design process – Hardware simulation – Levels of abstraction – VHDL requirements – Elements of VHDL – Top down design VHDL operators – Timing – Concurrency – Objects and classes – Signal assignments – Concurrent and sequential assignments.

UNIT – IV  Structural, Data flow & Behavioral description of hardware in VHDL    

Parts library – Wiring of primitives – Wiring of iterative networks – Modeling a test bench – Top down wiring components – Subprograms. Multiplexing and data selection – State machine descriptions – Open collector gates – Three state bussing. - Process statement – Assertion statement – Sequential wait statements – Formatted ASCII I/O operations MSI based design.

UNIT – V   Introduction to Verilog HDL

Lexical conventions – Data types – System tasks and Compiler Directives- Modules and Ports- Gate Level Modeling with Examples.

References

  1. P.K. Chan & S. Mourad,  “Digital Design sing Field Programmable Gate Array” 1st Edition, Prentice Hall, 1994.

  2. J. V. Old Field & R.C. Dorf,  “ Field Programmable Gate Array”, John Wiley, 1995.   

  3. M. Bolton, “ Digital System Design with Programmable Logic”,   Addison Wesley, 1990.

  4. Thomas E. Dillinger,  “ VLSI Engineering”,  Prentice Hall, 1st Edition, 1998.

  5. Douglas Perry,   “VHDL”, 3rd Edition, McGraw Hill 2001.

  6. J. Bhasker,   “VHDL”, 3rd Edition, Addison Wesley, 1999.

MVLD106R01 – MODELLING   LAB

L - 0, T - 0, P - 6

    List of Experiments using VHDL

Simple Design exercises:

01   Half adder, Full adder, Subtractor Flip Flops, 4bit comparator.

02   Parity generator

03   Bit up/down counter with load able count

04   Decoder and encoder

05   8 bit shift register

06   8:1 multiplexer

07   Test bench for a full adder

08   Barrel shifter

09   N by m binary multiplier

10   RISC CPU (3bit opcode, 5bit address)

TOOLS : 

Xilinx Tools, Cadence Tools, Model SIM, Leonardo Spectrum Tools shall be used.

MVLD107R02 – DESIGN  LAB  I

L - 0, T - 0, P - 3

    List of Experiments

 

1.      Introduction to layout design rules

2.      Layout of basic logic gates

3.      Layout of any combinational circuit

4.      Introduction to SPICE simulation and coding

 

Tools used : Cadence tools, Mentor Graphics tools.

 

MVLD201R01 VLSI SYSTEM DESIGN AND TESTING

L - 4, T - 0, P - 0 ( 60 Periods )

Unit - I   CMOS SUBSYSTEM DESIGN

Introduction – Data path operations –Parity generator – Comparators – Zero/one detectors- Binary counters – Boolean operations – Multiplication – Shifters.

UNIT - II   MEMORY ELEMENTS

Read/write memory :- RAM- Register files – FIFOs, LIFOs, SIPOs- Serial Access memory. Read only memory – Content Addressable memory - Finite – State Machine – FSM Design procedure – Control Logic implementation :- PLA Control implementation – ROM Control implementation – Multilevel logic – An example of control logic implementation.

UNIT - III   TESTING OF COMBINATIONAL  CIRCUITS

Faults in digital circuits – Failures and faults – Modeling of faults – Temporary faults – Test generation for Combinational logic circuits – testable combinational logic circuit design – Scan based design and JTAG testing issues.

UNIT - IV   TESTING OF  SEQUENTIAL CIRCUITS

Test generation for sequential circuits – Design of testable sequential CK5- Built in self test – Testable memory design.

UNIT - V   VERIFICATION AND TESTING

Verification – Timing verification – Testing concepts –  Fault coverage – ATPG – Types of tests – Testing FPGAs – Design for testability.

Reference Books

1.        N.H.E.Weste and K.Eshraghian, “ Principles of CMOS VLSI Design”, 2nd Edition  - Addition Wesley,1993.

2.        Jan .M.Rabaey, “Digital Integrated Circuits a design perspective” , PHI 1st Edition, 1995.

MVLD202R01 ANALOG VLSI

L - 4, T - 0, P - 0 ( 60 Periods )

UNIT –I

Basic current mirrors and single stage amplifiers – simple cmos current mirror – common source – common gate amplifier with current mirror active load – source flower with current mirror to supply bias current – high output impedance current mirrors and bipolar gain stages – frequency response.

UNIT – II

Operational amplifier design and compensation: two stage CMOS operational amplifier – feedback and operational amplifier compensation – advanced current mirrors – folded-cascode operational amplifier – current mirror operational amplifier – fully differential operational amplifier – common mode feedback circuits – current feedback operational amplifier. Comparator – charge injection error – latched comparators – BiCMOS comparators.

UNIT –III

Sample and hold and switched capacitor circuits : MOS, cMOS and biMOS sample and hold circuits – switched capacitor circuits – basic operation and analysis first order and biquad filters – charge injection – switched capacitor gain circuit – correlated double sampling techniques – other switched capacitor circuits.

UNIT – IV

Data converters : ideal d/a and a/d converters – quantization noise – performance limitations. nyquist rate d/a converters – decoder based converters – binary scaled converters – hybrid converters. nyquist rate a/d converters – integrating – successive approximation – cyclic flash type – two step interpolating – folding and pipelined – a/d converters.

UNIT – V

Over sampling converters and filters : over sampling with and without noise haping – digital decimation filter – high order modulators – band pass over sampling converters – practical considerations – continuous time filters – mixers – PLLs - multipliers.

References

1.      D.A. John  and Ken Martin , “analog integrated circuit design” , John Wiley, 1st Edition, 1996.

2.      Mohamed Ismail, “Analog VLSI” , Mc Graw hill,  1st Edition, 1994.

MVLD 203R01 - COMPUTER AIDED DESIGN FOR VLSI

L - 3, T - 0, P - 0 ( 45 Periods )

UNIT – I   Basic Algorithms and Data structures

Data Structures and Basic Algorithms – Algorithmic Graph Theory and Computational complexity – Tractable and Intractable problems - General Purpose Methods for Combinational Optimization.                                      

UNIT – II   Partitioning – Floor planning – Placement & Routing Algorithms  

Partitioning – problem formulation – classification of partitioning algorithms – group migration algorithms – simulated annealing and evolution – performance driven partitioning - floor planning and pin assignment – problem formulation – classification of floor planning algorithms – classification of pin assignment algorithms – placement – problem formulation – classification of placement algorithms – simulation based placement – partitioning based placement – performance driven placement – routing – global routing – problem formulation – classification of global routing algorithms – detailed routing – problem formulation – classification of detailed routing algorithms.

UNIT – III   Simulation, Logic synthesis & Verification  

Simulation – Different levels of simulation - Logic synthesis & Verification – basic issues in combinational logic synthesis – binary decision diagrams - ROBDD principles – implementation and construction – manipulation – variable ordering –applications to verification and combinatorial optimization.

UNIT – IV   High level synthesis & Compaction  

Hardware models for high level synthesis – internal representation of the input algorithm – allocation, assignment and scheduling -  Compaction – problem formulation – classification of compaction algorithms – one dimensional compaction – one and a half dimensional compaction – two dimensional compaction – hierarchical compaction – recent trends in compaction.

UNIT – V   Physical Design Automation of FPGAs & MCMS

Physical Design Automation of FPGAs – FPGA technologies – physical design cycle for FPGAs – partitioning – routing - Physical design automation of MCMS – MCM technologies – MCM Physical design cycle – partitioning – placement – routing -VHDL - Verilog - implementation of simple circuits using VHDL and Verilog.

References

  1. N.A.Sherwani, “Algorithms for VLSI Physical Design Automation”, 3rd Edition, Kluwer Academic,1999.

  1. S.H.Gerez, “Algorithms for VLSI Design Automation”, John Wiley, 1998.

MVLD206R01 - DESIGN  LAB  II

L - 0, T - 0, P - 3

List of Experiments 

  1. SPICE simulation of basic analog circuits.

  2. Analog Circuit simulation using Cadence tools

  3. Verification of layouts (DRC, LVS)

  4. Back annotation

 Tools used : Cadence tools, Mentor Graphics tools

MVLD207R01 - Mini Project

L - 0, T - 0, P - 6

Top 


 

Copyright © TIFAC-CORE at SASTRA  Deemed University, webmaster@sastra.edu